The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventor, to the extent that it is described in this background section, as well as aspects of the description that does not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Double data rate type three synchronous dynamic random access memory (DDR3 SDRAM) is a memory interface specification. One advantage of DDR3 SDRAM is the ability to transfer data at eight times the speed of the DRAM's internal memory arrays. Once a row is opened in the memory, the row is accessed at up to 100% utilization of the memory's internal bandwidth. But there are various overhead penalties associated with certain access scenarios in DDR3 SDRAM. A typical DDR3 SDRAM has eight internal memory banks, each with perhaps 2000 pages or rows. Every time a new row is opened within a memory bank, an open row within the memory bank is first closed, which impacts the performance of the SDRAM. It takes nine cycles to open up a new page in a DDR3 SDRAM. Other access patterns also result in overhead penalties. Thus, random access of DDR3 SDRAM results in real-world performance that is less than the theoretical maximum throughput and bandwidth. Bank interleaving, is a partial solution to this problem.